In one conventional data storage arrangement, a host includes a host bus adapter (HBA) that is coupled to a target data storage device. The HBA exchanges data and commands with the target. The commands and data transmitted from the host to the target are first temporarily stored in a transmit queue in the HBA, and thereafter, a packet engine in the HBA transmits the queued commands and data to the target.
In this conventional arrangement, the HBA exchanges commands and data with the target in accordance with Serial Advanced Technology Attachment II (SATA II) protocol. SATA II protocol provides Native Command Queuing (NCQ) transactions that include four phases: command phase, register update phase, data phase, and completion phase. In order to comply with SATA II protocol, constraints are imposed on transmissions of commands and data in these phases. For example, after commencement of an NCQ data phase, no commands should be sent from the host to the target until after the data phase has been fully serviced, and only data that is properly associated with the data phase should be exchanged between the host and target. Also in order to comply with SATA II protocol, if the target indicates an error condition during an NCQ completion phase, no commands should be sent from the host to the target until after the host clears the target's error condition.
Unfortunately, depending upon the particular capabilities of the packet engine, the packet engine may be unable to distinguish between (1) commands and data stored in the transmit queue, and/or (2) data associated with a particular data phase and other data (e.g., associated with one or more other data phases) stored in the transmit queue. As a result, this conventional arrangement may enter a race condition in which the packet engine may transmit commands and/or data, when it is inappropriate to do so, given the above constraints of SATA II protocol. This may result in the target entering an unstable or metastable operating state, locking up of the target and/or host, and/or in corruption of data at the target (e.g., if the data phase was intended to involve a write of data from the host to the target).
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.